Television display system with increased field frequency

ABSTRACT

In accordance with the present invention, a read clock frequency applied to field memories (16a) and (16b) comprising a converting circuit (16) which converts the field frequency of a video signal is changed at the unit of a vertical cycle whereby vertical cycles of video signals read out from the field memories (16a) and (16b) are made substantially equal to one another. Accordingly, a horizontal deflecting current waveform on which a parabolic wave current of, for example, the vertical cycle is superposed becomes equal during each vertical period so that it becomes possible to prevent a jitter from being produced at right and left ends of a picture screen.

TECHNICAL FIELD

The present invention relates to a television receiver which displays atelevision picture at, for example, field frequency twice the normalfield frequency.

BACKGROUND ART

In the existing television system, a so-called interlaced scanningsystem is carried out. That is, one picture (frame) is transmitted bytwo vertical scannings (fields). This interlaced scanning system isconsidered in order to increase the number of scanning lines as much aspossible in a limited frequency band without a flicker being perceivedby a viewer.

However, in the CCIR system employed mainly in European countries, thefield frequency is 50 Hz. By this frequency, the flicker can not beremoved completely and the flicker becomes conspicuous particularly whenthe brightness of the television picture is high.

Therefore, in the prior art, such a television receiver is proposed thata television picture is displayed at a field frequency twice the normalfield frequency. FIG. 1 shows an example thereof.

In the figure, reference numeral 1 designates an antenna, 2 a tuner, 3 avideo intermediate frequency amplifier, and 4 a video detecting circuit.The video detecting circuit 4 produces a video signal Sv of interlacedsystem of 625 lines/50 fields and 2:1.

This video signal Sv is converted to a digital signal by an A/Dconverter 5 and then fed to a converting circuit 6 so as to be convertedto a field twice normal speed video signal with field frequency twicethe normal field frequency.

The converting circuit 6 is formed of field memories (random accessmemories having a storage capacity of picture elements of one fieldperiod (1V)) 6a and 6b and switching circuits 6c and 6d. The switchingcircuit 6c is changed in position to the sides of the memories 6a and 6bat every field period 1V, while the switching circuit 6d is changed inposition reversely. The memory selected by the switching circuit 6c issupplied with a write clock pulse having a timing corresponding to theaboye-described picture elements, while the memory selected by theswitching circuit 6d is supplied with a read clock pulse with frequencytwice the frequency of the write clock pulse.

The video signal Sv converted to the digital signal by the A/D converter5 is supplied through the switching circuit 6c to the memories 6a and 6bby one field each at every field period 1V in which it is written. Thevideo signal of one field amount, which is written in the memories 6band 6a during a field period 1V just before the above-mentioned fieldperiod, is read out therefrom continuously twice with a cycle of 1/2 V.This video signal is derived through the switching circuit 6d. In otherwords, the switching circuit 6d delivers a field twice normal speedvideo signal Sv, that is, at a double field frequency.

This video signal Sv' is converted to an analog signal by a D/Aconverter 7 and then fed to a signal processing circuit 8. Then, fromthe signal processing circuit 8, red, green and blue primary colorsignals R, G and B are produced and then supplied to an image receivingtube 9, respectively.

The video signal Sv derived from the video detecting circuit 4 issupplied to a vertical synchronizing separating circuit 10. A verticalsynchronizing signal Pv derived from the separating circuit 10 ismultiplied twice by a frequency multiplier 11 to be a signal withfrequency twice the ordinary frequency. This signal is supplied througha vertical deflecting circuit 12 to a deflecting coil 13.

The video signal Sv' derived from the D/A converter 7 is supplied to ahorizontal synchronizing separating circuit 14. A horizontalsynchronizing signal P_(H) ' (having the frequency twice the normalfrequency) derived from the separating circuit 14 is supplied through ahorizontal deflecting circuit 15 to the deflecting coil 13.

Since the example of the television receiver shown in FIG. 1 isconstructed as described above, the primary color signals R, G and Beach of which has the field frequency twice the normal field frequencyare supplied to the picture receiving tube 9 and the horizontal andvertical deflection scannings are carried out at scanning speed twicethe normal scanning speed, and hence a color picture with the fieldfrequency twice the normal field frequency is displayed on the picturereceiving tube 9. Accordingly, also in the above CCIR system, the fieldfrequency becomes 100 Hz which is twice the normal field frequency sothat the viewer feels no flicker.

In the case of the example shown in FIG. 1, however, the horizontalsynchronization of the video signal Sv' derived from the convertingcircuit 6 is disturbed cyclically so that a distortion occurs in theupper portion of the picture screen.

That is, the write-in state of the video signal Sv derived from thevideo detecting circuit 4 in the memories 6a and 6b is expressed asshown in FIG. 2A, in which references F₁ and F₂ designate first andsecond fields, respectively. The video signal Sv' from the convertingcircuit 6 is expressed as shown in FIG. 2B. In the figure, arrowsrepresent the positions of the vertical synchronizing signals. As willbe clear from FIG. 2B, in the video signal Sv', the phase of thehorizontal synchronization is displaced by 180° at every two fields, orat every 1/50 seconds (shown by broken line arrows), whereby thesynchronization on the upper portion of the picture screen is disturbed,resulting in a picture distorion.

Therefore, the present applicant has proposed a television receiverwhich is free of such picture distortion and FIG. 3 shows an examplethereof. In FIG. 3, like parts corresponding to those of FIG. 1 aremarked with the same references.

In the figure, the video signal Sv derived from the video detectingcircuit 4 is converted to the digital signal by the A/D converter 5 andthen fed to a converting circuit 16 so as to be converted to the fieldtwice normal speed video signal with the frequency twice the normalfield frequency.

The converting circuit 16 is formed of field memories (random accessmemories) 16a and 16b having storage capacities of picture elements of313 horizontal periods (313H) and 312 horizontal periods (312H) andswitching circuits 16c and 16d. The switching circuit 16 is changed inposition alternately to the side of the memory 16a during each period of313H and to the side of the memory 16b during each period of 312H, whilethe switching circuit 16d is changed in position in the reverse manner.These change-overs of the change-over switches 16c and 16d arecontrolled by a control circuit 17. This control circuit 17 is suppliedwith horizontal and vertical synchronizing signals P_(H) and P_(V) whichare separated from the video signal Sv by a synchronizing separatingcircuit 18.

The memory selected by the switching circuit 16c is supplied with thewrite clock pulse having the timing corresponding to the above pictureelements, while the memory selected by the switching circuit 16d issupplied with a read clock pulse with the frequency twice the frequencyof the write clock pulse.

The video signal Sv converted to the digital signal by the A/D converter5 is supplied through the switching circuit 16c to the memories 16a and16b in which it is alternately written during each period of 313H and312H. FIG. 4A shows the write-in state of the memories 16a and 16b, inwhich references F₁ and F₂ represent the first and second fields,respectively. During the periods of 313H and 312H in which the videosignal is being written in one of the memories, the video signal writtenin the other of the memories 16b and 16a during the periods just beforethe above 312H and 313H are read out therefrom twice continuously. Thissignal is derived through the switching circuit 16d as a field twicenormal speed video signal Sv*. FIG. 4B shows the video signal Sv* whichis derived through the switching circuit 16d, in which the fieldportions corresponding to those of FIG. 4A are marked with the samereferences. By the way, due to the difference between the write time andthe read time, extra or lack of one line amount per field is produced inthe video signal Sv*.

In FIG. 4B, at the portions of, for example, the F₁ and F₁ fields (theportions read out from the memory 16a), 313 lines are not read outbecause of a time relation. Further, at, for example, the F₂ and F₂field portions (the portions read out from the memory 16b), the videosignal of one line amount is lacked and during that period, the readingoperation is stopped and the video signal of one line amount is lacked(shown by one-dot chain lines). The extra and lack of the video signalof one line amount as mentioned above occur in the vertical blankingperiod so that in practice, this does not disturb the televisionpicture.

The writing in and reading out from the memories 16a and 16b arecontrolled by the control circuit 17.

The video signal Sv* derived from the switching circuit 16d is convertedto the analog signal by the D/A converter 7 and then fed to the signalprocessing circuit 8. Then, the red, green and blue primary colorsignals R, G and B are produced from the signal processing circuit 8 andthen fed to the picture receiving tube 9, respectively.

The control circuit 17 produces a vertical synchronizing signal Pv* atthe timing shown by arrows in FIG. 4B. More particularly, the verticalsynchronizing signal Pv* is produced at the beginning of the first F₁field, at the timing after 312 lines from the preceding line, namely, atthe beginning of the second F₁ field, at the timing after 311.5 linesfrom the preceding line, at the timing after 313 lines from thepreceding line and at the timing after 313.5 lines from the precedingline, or the beginning of the first F₁ field, hereinafter similarly.This synchronizing signal Pv* is supplied through the verticaldeflecting circuit 12 to the deflecting coil 13 which then carries outthe vertical deflection scanning. When the synchronizing signal Pv* isproduced at the above-mentioned timing, in the same F₁ field and F₂fields, the scanning lines are formed at the same positions and thescanning lines respectively formed at the F₁ field and F₂ field aredisplaced by 1/2 scanning line spacing each. In other words, theinterlaced relation of the video signal Sv is kept as it is.

The video signal Sv* from the D/A converter 7 is supplied to thehorizontal synchronizing separating circuit 14. A horizontalsynchronizing signal P_(H) * (having the frequency twice the normalfrequency) derived from the separating circuit 14 is supplied throughthe horizontal deflecting circuit 15 to the deflecting coil 13 by whichthe horizontal deflection scanning is carried out.

According to the example of the television receiver shown in FIG. 3, thehorizontal synchronization of the video signal Sv* becomes continuous asshown in FIG. 4B so that the synchronization can be prevented from beingdisturbed by the insuccessive horizontal synchronization unlike theexample of FIG. 1 and thus no picture distortion is produced.

However, in the example of FIG. 3, since the generation timing of thevertical synchronizing signal Pv* is determined such that the scanninglines of the same F₁ fields and F₂ fields are formed at the samepositions (see the arrows in FIG. 4B), the vertical cycle is madedifferent very slightly and not becomes exactly 1/100 second=10 m sec.

By the way, in the television receiver, in order to correct left andright pincushion distortions, a parabolic wave current with the verticalsynchronizing frequency is superposed on the horizontal deflectioncurrent. In this case, since the cycle of the vertical synchronizingsignal Pv* is different (see FIG. 5A) as mentioned above, also thevertical deflection current becomes correspondingly different (see FIG.5B). Further, the horizontal deflection current waveform is changed atevery vertical cycle (see FIG. 5C). As described above, since thehorizontal deflection current waveform is different, a jitter appears inthe right and left ends of the picture screen at a fundamental frequencyof 25 Hz (four field cycles of F₁, F₁, F₂, and F₂). This jitter becomesconspicuous much if the deflection angle becomes larger.

To remove this jitter, it may be considered to correct the horizontaldeflection current waveform by the deflecting system. However, thecorrection thereof is very difficult and requires a special deflectioncorrecting circuit.

In this case, since the cycle of the vertical synchronizing signal Pv*becomes different (see FIG. 5A), also the vertical deflecting currentbecomes different at every vertical cycle (see FIG. 5B) but this doesnot exert so serious bad influence on the picture screen.

DISCLOSURE OF INVENTION

The present invention is to prevent a jitter from being produced at theright and left ends of a picture screen without providing a specialdeflection correcting circuit. To achieve this object, the presentinvention is to change the read clock frequency for a field memory whichforms a converting circuit for converting the field frequency at theunit of vertical cycle and to make each vertical cycle of a video signalread out from the field memory substantially equal. Thus, the horizontaldeflecting current waveforms become equal to each other in each verticalcycle so that a jitter can be prevented from being produced at the rightand left ends of the picture screen.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1 and 3 are respectively block diagrams showing prior artexamples,

FIGS. 2A, 2B, 4A, 4B, 5A, 5B and 5C are respectively diagrams useful forexplaining the prior art examples,

FIG. 6 is a block diagram showing an embodiment of a television receiveraccording to the present invention,

FIG. 7 is a diagram showing a practical example of a PLL circuit,

FIG. 8 is a block diagram showing another embodiment of the televisionreceiver according to the present invention and

FIG. 9 is a diagram useful for the explanation thereof.

BEST MODE FOR CARRYING OUT THE INVENTION

An embodiment of a television receiver according to the presentinvention will hereinafter be described with reference to FIG. 6. InFIG. 6, like parts correspocding to those of FIG. 3 are marked with thesame references and will not be described in detail.

In this embodiment, the duration of the period of 312 lines (hereinafterreferred to as A field) from the beginning of the first F₁ field, theduration of the period of 311.5 lines (hereinafter referred to as Bfield) after the preceding period, the duration of the period of 313lines (hereinafter referred to as C field) after the preceding periodand the duration of the period of 313.5 lines (hereinafter referred toas D field) after the preceding period shown in FIG. 4B or therespective vertical cycles become equal to 1/100 sec=10 m sec.

In FIG. 6, reference numeral 19 designates a PLL circuit. This PLLcircuit 19 is supplied with the horizontal synchronizing signal P_(H)from the synchronizing separating circuit 18 and produces at its outputside a signal with the frequency of, for example, 1250 f_(H) (f_(H) isthe horizontal frequency). This signal is supplied through a frequencydivider 20 having a frequency dividing ratio of 2 to a write addresscounter 21 as its write clock pulse. A write address W_(AD) from thecounter 21 is supplied through a switching circuit 22 to the memories16a and 16b. In this case, the PLL circuit 19 is constructed as, forexample, shown in FIG. 7. In the figure, reference numeral 23 designatesa phase comparator, 24 a low-pass filter, 25 a voltage-controlled typevariable frequency oscillator and 26 a 1/N-frequency divider. In thiscase, N=1250 is established.

In FIG. 6, reference numerals 27, 28, 29 and 30 designate PLL circuitsand they produce read clock pulses CL_(A), CL_(B), CL_(C), and CL_(D) ofA, B, C and D fields, respectively. These PLL circuits 27 to 30 aresupplied with the horizontal synchronizing signal P_(H) from thesynchronizing separating circuit 18.

By the way, in this embodiment, since the periods of the A to D fieldsare made equal to 10 m sec as mentioned above, if the frequencies of theclock pulses CL_(A), CL_(B), CL_(C) and CL_(D) produced from the outputsides of the PLL circuits 27, 28, 29 and 30 are respectively taken asf_(A), f_(B), f_(C) and f_(D), the following relation is established.##EQU1## Further, each frequency of these clock pulses CL_(A) to CL_(D)is selected to be substantially twice the frequency of the write clockpulse.

Accordingly, in this embodiment, the frequencies f_(A), f_(B), f_(C) andf_(D) of the clock pulses CL_(A), CL_(B), CL_(C) and CL_(D) are selectedto be 1248 f_(H), 1246 f_(H), 1252 f_(H) and 1254 f_(H), respectively.In this case, also the PLL circuits 27, 28, 29 and 30 are constructedas, for example, shown in FIG. 7, in which N=1248, 1246, 1252 and 1254are respectively established.

The clock pulses CL_(A), CL_(B), CL_(C) and CL_(D) from these PLLcircuits 27, 28, 29 and 30 are respectively supplied to a switchingcircuit 31 and the switching circuit 31 delivers the clock pulsesCL_(A), CL_(B), CL_(C) and CL_(D) during the periods of the A, B, C andD fields. The clock pulse derived from the switching circuit 31 issupplied to a read address counter 32. A read address R_(AD) from thecounter 32 is supplied through the switching circuit 22 to the memories16a and 16b. In this case, of the memories 16a and 16b, the memory setin the write mode by the switching circuit 22 is supplied with the writeaddress W_(AD), while the memory set in the read mode thereby issupplied with the read address R_(AD).

In FIG. 6, reference numeral 33 designates a pincushion distortioncorrecting circuit, by which a parabolic wave current of verticalsynchronizing frequency for use in correcting a pincushion distortion issuperposed upon the horizontal deflecting current.

Other circuit elements are formed similarly to those of the exampleshown in FIG. 3.

This embodiment is constructed as mentioned above, in which during theA, B, C and D fields, the different read clock pulses CL_(A), CL_(B),CL_(C) and CL_(D) are supplied respectively and the periods of these A,B, C and D fields, or the respective vertical periods become equal to 10m sec so that the horizontal deflecting current waveform on which theparabolic wave current of the vertical synchronizing frequency forcorrecting the right and left pincushion distortions in each verticalperiod is superposed becomes equal, thus removing such a defect that thejitter is produced at the right and left ends of the picture screenunlike the example of FIG. 3. Accordingly, in this embodiment, it is notnecessary to provide the special correcting circuit.

By the way, as described above, since the periods of the A, B, C and Dfields become 10 m sec equally, the horizontal cycle of each fieldbecomes different. This difference is, however, very small and can beneglected.

FIG. 8 shows another embodiment of this invention. In FIG. 8, like partscorresponding to those of FIG. 6 are marked with the same references.

In the embodiment shown in FIG. 8, the timing at which the verticalsynchronizing signal Pv* is produced is selected to be the timing shownby arrows in FIG. 9. That is, at the timing of the beginning of thefirst F₁ field, at the timing with a delay of 312 lines after thepreceding timing, at the timing with the delay of 312.5 lines after thepreceding timing, at the timing with a delay of 313 lines after thepreceding timing and at the timing with a delay of 312.5 lines after thepreceding timing, or at the timing of the beginning of the first F₁field and at the similar timing the vertical synchronizing signal Pv* isproduced hereinafter.

When the vertical synchronizing signal Pv* is produced at such timings,the scanning line of the F₂ field is displaced upward by one scanningline as compared with the example of FIG. 6. This problem, however, canbe solved by delaying the signal supplied to the picture receiving tube9 by one line amount during the F₂ field or shifting the whole of thesignal by one scanning line to the underside during the F₂ field.

In the embodiment of FIG. 8, the duration of the period of 312 lines(hereinafter referred to as A' field) from the beginning of the first F₁field, the duration of the period of 312.5 lines (hereinafter referredto as B' field) after the preceding period, the duration of the periodof 313 lines (hereinafter referred to as C' field) and the duration ofthe period of 312.5 lines (hereinafter referred to as D' field) afterthe preceding period, or the respective vertical cycles become 1/100sec=10 m sec equally.

In FIG. 8, reference numerals 34, 35 and 36 respectively designate PLLcircuits which produce read clock pulses CL_(B) '.sub.(D) ', CL_(A) 'and CL_(D) ' for the periods B'(D'), A' and C'. These PLL circuits 34 to36 are supplied with the horizontal synchronizing signal P_(H) from thesynchronizing separating circuit 18.

In the embodiment of FIG. 8, since the periods of A' to D' fields become10 m sec equally, if the frequencies of the clock pulses CL_(B)'.sub.(D) ', CL_(A) ' and CL_(C) ' produced from the output sides of thePLL circuits 34, 35 and 36 are respectively taken as f_(B) '.sub.(D) ',f_(A) ' and f_(C) ', the following relation can be established. ##EQU2##Accordingly, in this embodiment of FIG. 8, the frequencies f_(B)'.sub.(D) ', f_(A) ' and f_(C) ' of the clock pulses CL_(B) '.sub.(D) ',CL_(A) ' and CL_(C) ' are respectively selected to be 1250 f_(H), 1248f_(H) and 1252 f_(H).

The clock pulses CL_(B) '.sub.(D) ', CL_(A) ' and CL_(C) ' from thesePLL circuits 34, 35 and 36 are respectively supplied to a switchingcircuit 37 and the switching circuit 37 delivers clock pulses CL_(B)'.sub.(D) ', and CL_(A) ' and CL_(C) ' during the field periods ofB'(D'), A' and C'. The clock pulses derived from the switching circuit37 are supplied to the read address counter 32.

In FIG. 8, the clock pulse CL_(B) '.sub.(D) ' derived from the PLLcircuit 34 is supplied through the frequency divider 20 to the writeaddress counter 21 as the write clock pulse therefor.

Other circuit elements are formed similarly to those of the exampleshown in FIG. 6.

The embodiment of FIG. 8 is constructed as described above. Accordingly,during the respective B'(D'), A' and C' fields, the different read clockpulses CL_(B) '.sub.(D) ', CL_(A) ' and CL_(C) ' are suppliedrespectively so that the periods of respective A', B', C' and D' fields,or the respective vertical periods become 10 m sec equally. Therefore,the horizontal deflecting current waveforms in the respective verticalperiods become equal so that it becomes possible to achieve the similaraction and effect to those of the example of FIG. 6.

The frequencies of the write clock pulse and the read clock pulse arenot limited to those of the above-described embodiments but may be, forexample, twice the above frequencies. While in the above-mentionedembodiments the interlaced scanning system of the video system of 625lines/50 fields and 2:2 is explained, the present invention is notlimited to the above system but can be applied similarly to otherinterlaced scanning system of the other video signal. While in theabove-described embodiments the field frequency is selected to be twice,the present invention is not limited to the above field frequency butcan be similarly applied to a case in which the field frequency ischanged to be three times, four times, . . .

EFFECT OF THE INVENTION

According to the present invention as mentioned above, since therespective vertical cycles are made substantially equal, the horizontaldeflecting current waveform on which the parabolic wave current of, forexample, the vertical cycle is superposed becomes equal during eachvertical period so that the jitter is not produced at the right and leftends of the picture screen. Accordingly, no such special correctingcircuit for removing the jitter is required.

We claim:
 1. A television receiver cmprising: scan converter meansincluding field-memory means supplied with an input video signal of aninterlaced television system having a selected plurality of fields persecond, memory control means for supplying writing and reading signalsto said field-memory where the frequency of said reading signal isdifferent from that of said writing signal, thereby providing anincreased plurality of fields per second greater than said selectedplurality of fields, an output terminal for deriving an output videosignal; and a video display means supplied with said output videosignals, charaterized by a synchronizing signal separating circuit forseparating synchronizing signals from said input video signals and bymeans provided in said memory control means for changing the frequencyof said reading signal at a vertical rate including phase-lock loopmeans receiving said separated synchronizing signals and producingtherefrom a plurality of read clock pulse signals of selected differentfrequencies and a switching circuit receiving said plurality of readclock pulse signals for delivering said plurality of read clock pulsessignals to said field-memory means during corresponding periods ofrespective ones of said increased plurality of fields, whereby verticalintervals of odd fields of said output video signal are madesubstantially same as vertical intervals of even fields of said outputvideo signal.